Current-steering digital-to-analog converters (DACs), especially those implemented using metal oxide semiconductor (MOS) technology, are useful in converting digital signals into analog signals at a relatively high rate. Current-steering DACs are also configured to generate a differential output in order to better reduce noise, increase its output power, and suppress even order harmonics. Although current-steering DACs are useful and generally provide acceptable performance, they also suffer from being susceptible to third order harmonic distortion and higher order distortions, as explained with reference to the following examples.
FIG. 1 illustrates a schematic diagram of an exemplary current-steering DAC 100. The current-steering DAC 100 typically comprises a plurality of current-steering segments 102-1 through 102-N. Each current-steering segment is adapted to direct current to either the positive output terminal (OUTP) or the negative output terminal (OUTN) based on a complementary control signal, such as D1 and DB1 for segment 102-1 and Dn and DBn for segment 102-N. A binary-to-thermometer code decoder is typically employed to generate the complementary control signal from an input digital signal, which the DAC 100 converts into an output analog signal.
Each current-steering segment (e.g., 102-1 and 102-N) comprises a first transistor (e.g., M1 and M5), a second transistor (e.g., M2 and M6), and a pair of differential transistors (e.g., M3/M4 and M7/M8). The source of the first transistor (e.g., M1 and M5) is coupled to a power supply voltage (AVDD). The drain of the first transistor (e.g., M1 and M5) is coupled to the source of the second transistor (e.g., M2 and M6). The drain of the second transistor (e.g., M2 and M6) is coupled to the sources of the differential transistor pair (e.g., M3/M4 and M7/M8). The positive output terminal (OUTP) of the current-steering DAC 100 is taken off the drain of one of the differential transistor pair (e.g., M3 and M7, the transistors driven by complementary signal D1 and Dn). The negative output terminal (OUTN) of the current-steering DAC 100 is taken off the drain of the other differential transistor pair (e.g., M4 and M8, the transistors driven by complementary signal DB1 and DBn).
The first transistor (e.g., M1 and M5) of each current-steering segment (e.g., 102-1 and 102-N) serves to the set the amount of current flow through the segment in response to a VGATE control signal applied to its gate. The second transistor (e.g., M2 and M6) serves as a cascode device to set the steady-state output impedance of each segment in response to a VCASC control signal applied to its gate. The differential transistor pair (e.g., M3/M4 and M7/M8) serve to steer the segment current to either the positive output terminal (OUTP) or the negative output terminal (OUTN) in response to the complementary control signal (e.g., D1/DB1 and Dn/DBn). The node corresponding to the drain of the second transistor (or sources of the differential transistor pair) is typically referred to as the summing node (e.g., nodes S1 and Sn).
The current-steering DAC 100 is susceptible to third order harmonic distortion as the result of the switching of the differential transistor pair. In particular, prior to a switching event, the positive output terminal (OUTP) may have a voltage different, and possibly substantially different, than the voltage on the negative output terminal (OUTN). During a switching event, the voltage on the summing node will change due to a finite output impedance of the transistors in the differential pair (e.g. M3/M4 and M7/M8). Because of the voltage change on the summing node, a charge transfer effect takes place which is further increased by the capacitance present at the summing node. The charge flowing to the capacitance affects the converter's output signal by creating or increasing third order harmonic distortion.
Additionally, during switching of one or more current-steering segments, the output impedance of the current-steering DAC 100 drops substantially for the instantaneous time associated with the switching. For instance, the output impedance of the segment during switching, measured differentially, is equal to 2/gds, where gds is the output conductance of transistors M3 and M4. This impedance is much lower than that of the fully switched differential transistor pair. For instance, the steady-state output impedance of the segment is determined by the cascode connection of the transistors in the segment, which is substantially higher than the output impedance during switching. This also affects the converter's output signal by creating or increasing third order harmonic distortion at the output of the DAC 100. Other distortions may further be caused by interaction of the DAC 100 with other components, such as DACs configured to generate higher resolution outputs in combination with a main DAC. This is better explained with reference to the following example.
FIG. 2 illustrates a block and schematic diagram of another exemplary DAC circuit 200. The DAC circuit 200 comprises a main current-steering DAC 202, a first least significant bit (LSB) current-steering DAC 204, and a second LSB current-steering DAC 206. The input digital signal applied to the DAC circuit 200 has a code length of M+N+K bits, where M represents the number of most significant bits (MSB), N represents the number of intermediate significant bits, and K represents the number of least significant bits (LSB). The main current-steering DAC 202 receives the most significant bits M of the input digital word. The first LSB current-steering DAC 204 receives the intermediate significant bits N of the input digital word. The second LSB current-steering DAC 206 receives the least significant bits K of the input digital word.
The main current-steering DAC 202 has 2M−1 current-steering segments and a full-scale output related to the full-scale code A of the input digital word. The first LSB current-steering DAC 204 has 2N−1 current-steering segments and a full-scale output related to the full-scale code A of the input digital word divided by 2M (i.e., ˜A/2M). The second LSB current-steering DAC 206 has K binary weighted current-steering segments and a full-scale output related to the full-scale code A of the input digital word divided by 2(M+N) (i.e., ˜A/2M+N). The positive output terminals (OUTP) of the DACs 202, 204, and 206 are coupled together. The negative output terminals (OUTN) of the DACs 202, 204, and 206 are coupled together.
In theory, the DACs 202, 204, 206 should be clocked at substantially the same time so that the currents from each of them timely combine at the output of the DAC circuit 200. However, in practice, there are typically clock timing difference and different length propagation paths at the input and outputs of the DACs that produce timing skew between the DACs. As a result, the timing skew produces a rich spectrum of high order harmonics, which rapidly increases as the DAC clock rate increases. The distortion caused by the timing skew may limit the DAC's signal to noise and distortion ratio (SNDR), and at higher update rates and lower output signal input amplitudes it may also limit the DAC's spurious free dynamic range (SFDR).